1. Field of the Invention
The invention relates to the test of memories.
2. Description of the Related Art
Today Built-In Self-Test (BIST) is the mainstream test technology for embedded memories. It has replaced the external testing of embedded memories because it solves some significant limitations of the latter, such as:                the cost of test equipment for testing complex systems on a chip (SOC) that includes both memory and logic,        the difficulties for applying in a non-scan design the highly sequential memory test algorithms by propagating test vectors through the various blocks surrounding an embedded memory,        the difficulties for applying one test per clock in a scan based design,        the difficulties for applying test vectors at-speed, caused by the lower speed of the external test equipment with respect to advanced chip designs, and by the long delays introduced by the interconnections of the board.        
The latter problem will be encountered even if a direct access mechanism is implemented between the inputs/outputs of the embedded memory and the inputs/outputs of the chip, which can be done for instance by using a multiplexing.
Since the BIST hardware is implemented in the same chip as the memory, all these problems are not encountered. Thus, the BIST can be used for testing embedded memories at their operation speed (at-speed). In addition, memory BIST reduces significantly the test cost of complex systems on a chip, since we can test a system on a chip including embedded memories by using an Automatic Test Equipment (ATE) designed for testing logic designs. However, BIST has a significant limitation with respect to external test equipment. In fact, once the BIST hardware has been implemented, we can test the memory only by means of the test algorithm implemented in the BIST hardware. This is not a significant drawback for situations where the memory design and the fabrication process have been stabilized, and there is enough experience for determining the basic defect types encountered for a given memory design and fabrication process and for developing a test algorithm that can guaranty the detection of these faults during manufacturing testing. Unfortunately, in many other situations conventional BIST is not a convenient approach. Such situations are for instance memory debugging for determining the principal fault types related to a new memory design and fabrication process.
Failure analysis on failed components returned from customers is another situation where the rigidity of conventional BIST is unsuitable.
Due to these problems, many companies implement a memory BIST for achieving at-speed testing of embedded memories, and use multiplexing for creating direct access on the inputs/outputs of the embedded memories, in order to maintain the flexibility in terms of test algorithms offered by external test equipment. Thus, BIST based testing can be used for fabrication testing, while external testing can be used to apply any test algorithm required for debugging and failure analysis. However, the debugging and failure analysis of faulty components returned from the field will not be performed at-speed, thus, reducing the efficiency of these tasks.
A solution for improving this situation is to implement a conventional BIST scheme that implements a large variety of test algorithms, but the cost of the BIST hardware can become prohibitive, and the test algorithms that can be executed after fabrication will be limited to those selected during the BIST implementation.